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US 2016/0260476 A1Published application
Programming Techniques for Non-Volatile Memories with Charge Trapping Layers
AssigneeSanDisk Technologies LLC
InventorsKenneth Louie, Man Mui
Life of this patent
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Abstract
Techniques are presented for the programming of a non-volatile memory in which multi-state memory cells use a charge trapping layer. When writing data onto a word lines, different data states are written individually, while programming inhibiting the other states, thereby breaking down the write operation into a number of sub-operations, one for each state to be written. This allows for improved timing and decreased power consumption.
Claims20
A method operating a non-volatile memory circuit having an array of memory cells each having a dielectric charge storage medium, a plurality of which are formed along a first word line, comprising:
- performing a programming operation to program a plurality of memory cells along the first word line from an initial state to one of a plurality of programmed states, the programmed states including first and second programmed states, where at least one of the memory cells along the first word line are to be programmed to each of the first and second programmed states, including:
- performing a first programming sub-operation, including:
- program inhibiting all memory cells not to be programmed to the first programmed state;
- program enabling all memory cells to be programmed to the first programmed state;
- and
- applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the first programmed state, wherein programmed enable memory cells that verify at the first programmed state are subsequently inhibited for subsequent programming pulses;
- and
- subsequently performing a second programming sub-operation, including:
- program inhibiting all memory cells not to be programmed to the second programmed state;
- program enabling all memory cells to be programmed to the second programmed state;
- and
- applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the second programmed state, wherein programmed enable memory cells that verify at the second programmed state are subsequently inhibited for subsequent programming pulses.
9 more elements
A non-volatile memory circuit, comprising:
- an array of memory cells each having a dielectric charge storage medium, a plurality of which are formed along a first word line;
- and
- programming and sensing circuitry connectable to the array whereby, when performing a programming operation to program a plurality of memory cells along the first word line from an initial state to one of a plurality of programmed states, the programmed states including first and second programmed states, where at least one of the memory cells along the first word line are to be programmed to each of the first and second programmed states, including:
- performing a first programming sub-operation, including:
- program inhibiting all memory cells not to be programmed to the first programmed state;
- program enabling all memory cells to be programmed to the first programmed state;
- and
- applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the first programmed state, wherein programmed enable memory cells that verify at the first programmed state are subsequently inhibited for subsequent programming pulses;
- and
- subsequently performing a second programming sub-operation, including:
- program inhibiting all memory cells not to be programmed to the second programmed state;
- program enabling all memory cells to be programmed to the second programmed state;
- and
- applying a series of programming pulses along the first word line, alternating with a set of verify operations for the memory cells to be programmed to the second programmed state, wherein programmed enable memory cells that verify at the second programmed state are subsequently inhibited for subsequent programming pulses.
11 more elements
Dependencies are inferred from the claim text.