Multiport memory cell having improved density area

A processor, comprising:

• a CPU;
• a memory component coupled to the CPU, wherein the memory component comprises a memory cell comprising:
• a data storing component comprising a plurality of load transistors;
• a first memory access component coupled to a first side of the data storing component;
• a second memory access component coupled to a second side of the data storing component;
• a plurality of lines coupled to the first memory access component and the second memory access component;
• and
• a read/write assist transistor coupled to the plurality of load transistors of the data storing component, wherein the plurality of load transistors is sized to prevent a change in a state of the data storing component until the read/write assist transistor is deactivated.

A method for accessing a memory cell, comprising:

• in a mode comprising write operation:
• biasing one or more bit lines to either a high or low voltage state;
• placing a high voltage level onto the gate of a memory access component;
• turning a read/write assist transistor on to impress the desired voltage level after the memory access component is turned off.