Improved sram storage unit based on dice structure

An improved SRAM memory cell based on a DICE structure comprising the following structure:

• an inerter structure for latch of logic level states, comprising a first inverter structure, a second inverter structure, a third inverter structure, and a fourth inverter structure;
• wherein the first inverter structure is formed through arranging a first PMOS transistor (P1) and a first NMOS transistor (N1) in series;
• the part between the drain of the first PMOS transistor (P1) and the drain of the first NMOS transistor (N1) serves as a first storage node (A);
• the second inverter structure is formed through arranging a second PMOS transistor (P2) and a second NMOS transistor (N2) in series;
• the part between the drain of the second PMOS transistor (P2) and the drain of the second NMOS transistor (N2) serves as a second storage node B;
• the third inverter structure is formed through arranging a third PMOS transistor (P3) and a third NMOS transistor (N3) in series;
• the part between the drain of the third PMOS transistor (P3) and the drain of the third NMOS transistor (N3) serves as a third storage node C;
• the fourth inverter structure is formed through arranging a fourth PMOS transistor (P4) and a fourth NMOS transistor (N4) in series;
• the part between the drain of the fourth PMOS transistor (P4) and the drain of the fourth NMOS transistor (N4) serves as a fourth storage node D;
• the first storage node (A) is connected with the gate electrodes of the second PMOS transistor and the fourth NMOS transistor;
• the second storage node (B) is connected with the gate electrodes of the first PMOS transistor and the third NMOS transistor;
• the third storage node (C) is connected with the gate electrodes of the fourth PMOS transistor and the second NMOS transistor;
• and
• the fourth storage node (D) is connected with the gate electrodes of the third PMOS transistor and the first NMOS transistor;
• a transmission structure, for transmitting logic level states stored in storage nodes and information from bit lines or bit bar lines, consisting of a fifth NMOS transistor (N5), a sixth NMOS transistor (N6), a seventh NMOS transistor (N7), and an eighth NMOS transistor (N8).