Power supply circuit and semiconductor memory device including the same
AssigneeSK hynix Inc.
InventorBon Kwang KOO
Life of this patent
Estimating the term…
Abstract
A power supply circuit includes a first transistor and a second transistor electrically coupled between a power supply terminal and an output terminal. When a first current path, in which output terminal through the first transistor, is formed, a voltage level of the output terminal may be controlled to be greater than or equal to a predetermined level. When a second current path, in which a current flows from the power supply terminal to the output terminal through the second transistor, is formed, the voltage level of the output terminal may be controlled to be less than or equal to the predetermined level.
Claims15
A power supply circuit, comprising:
- a first transistor and a second transistor electrically coupled between a power supply terminal and an output terminal,
- wherein when a first current path, in which a current flows from the power supply terminal to the output terminal through the first transistor, is formed, a voltage level of the output terminal is controlled to be greater than or equal to a predetermined level, and
- wherein when a second current path, in which a current flows from the power supply terminal to the output terminal through the second transistor, is formed, the voltage level of the output terminal is controlled to be less than or equal to the predetermined level.
A semiconductor memory device, comprising:
- a memory cell array including a plurality of memory cells;
- an input/output interface suitable for receiving data and a command from the external device;
- a page buffer suitable for receiving the data;
- a control logic suitable for receiving the command and generating a voltage supply control signal;
- and
- a power supply unit including a power supply device, and suitable for receiving the voltage supply control signal from the control logic, and supplying a memory driving voltage for driving the memory cell array,
- wherein a level of the memory driving voltage is determined based on a voltage level of the voltage supply control signal,
- wherein the power supply device includes a first transistor and a second transistor electrically coupled between a power supply terminal providing an input voltage and an output terminal outputting the memory driving voltage,
- wherein when a first current path, in which a current flows from the power supply terminal to the output terminal through the first transistor, is formed, a voltage level of the memory driving voltage is controlled to be greater than or equal to a predetermined level, and
- wherein when a second current path, in which a current flows from the power supply terminal to the output terminal through the second transistor, is formed, a voltage level of the memory driving voltage is controlled to be less than or equal to the predetermined level.
Dependencies are inferred from the claim text.