System and method for netlist clock domain crossing verification

An integrated circuit design verification system for performing clock domain crossing (CDC) verification of a netlist corresponding to a register-transfer-level (RTL) design of an integrated circuit, the system comprising a computer processor having access to data storage storing design verification software that, when executed by the computer processor, is operative to:

• receive, by the data storage, (a) a register-transfer-level (RTL) design of an integrated circuit, together with specified RTL-level CDC constraints, (b) RTL CDC verification results, and (c) a netlist corresponding to the RTL design;
• migrate, by the processor, the RTL-level-CDC constraints to netlist CDC constraints and store the migrated netlist CDC constraints in the data storage;
• check, by the processor, the received netlist for asynchronous clock domain crossings using the migrated netlist CDC constraints to identify correspondences between RTL and netlist level crossings and report any CDC violations found in the netlist;
• compare, by the processor, netlist CDC verification results with the received RTL CDC verification results and reporting specified kinds of similarities and differences;
• and
• store modifications to the netlist, in the data storage, that correct specified types of CDC violations.