US 2016/0259756 A1 · CIRCUITS AND METHODS FOR INTER-PROCESSOR COMMUNICATION

Abstract

Various example implementations are directed to circuits and methods for communicating between disparate processor circuits. According to an example implementation, a circuit arrangement includes a plurality of processor circuits and an inter-processor communication circuit. The inter-processor communication circuit is configured to provide, for each pair of the processor circuits, a respective communication channel between the pair of processor circuits. The inter-processor communication circuit includes a plurality of buffers including a respective first buffer and a respective second buffer for each communication channel. An access control circuit included in the inter-processor communication circuit is configured to restrict write access to the respective first buffer to the first processor circuit and restrict write access to the respective second buffer to the second processor circuit.

Claims20

Dependent claims

A system, comprising:

a plurality of processor circuits;
and
an inter-processor communication circuit coupled to the plurality of processor circuits and configured to provide, for each pair of the processor circuits, a respective communication channel between a first processor circuit of the pair to a second processor circuit of the pair, wherein the inter-processor communication circuit includes:
a plurality of buffers including for each respective communication channel, a respective first buffer and a respective second buffer;
and
an access control circuit coupled to the plurality of buffers and configured to, for the respective communication channel between the first processor circuit to the second processor circuit:
restrict write access to the first buffer to the first processor circuit;
and
restrict write access to the second buffer to the second processor circuit.

6 more elements

A method for communication between a plurality of processor circuits, comprising, for at least one pair of the plurality of processor circuits:

restricting write access to a respective first buffer for the pair to a first processor circuit of the pair;
restricting write access to a respective second buffer for the pair to a second processor circuit of the pair;
communicating messages from the first processor circuit of the pair to the second processor circuit of the pair via the respective first buffer;
and
communicating messages from the second processor circuit of the pair to the first processor circuit of the pair via the respective second buffer.

2 more elements

Dependencies are inferred from the claim text.

Circuits and methods for inter-processor communication

Life of this patent

Circuits and methods for inter-processor communication

Life of this patent

Abstract

Claims20