Static address allocation by passive electronics

A data bus node integrated circuit comprising:

• at least one static address selection terminal,
• a detecting circuit for detecting a state of the at least one static address selection terminal, and
• a communication circuit for receiving and/or transmitting data over a data bus and adapted for determining a node address identifier taking the detected state of the at least one static address selection terminal into account,
• wherein the detecting circuit is adapted for detecting the state of the at least one static address selection terminal by determining an electrical property of a passive electronic component when connected to said at least one static address selection terminal,
• wherein the detecting circuit is adapted for generating a signal indicative of an electrical resistance of a resistor when said resistor is connected to said at least one static address selection terminal,
• wherein said detecting circuit comprises an analog-to-digital converter or a time to digital conversion circuit for generating a signal indicative of said electrical property of said passive electronic component when connected to said at least one static address selection terminal, and switching means adapted for selectively routing either a signal from the at least one static address selection terminal or from an analog signal chain to said analog-to-digital converter or time to digital conversion circuit.

A method for statically addressing a plurality of data bus node integrated circuits on a data bus, the method comprising:

• connecting a plurality of data bus node integrated circuits to a data bus, each data bus node integrated circuit comprising at least one static address selection terminal,
• electrically connecting the at least one static address selection terminals of the data bus node integrated circuits to corresponding passive electronic components such as to provide a unique state or unique combination of states on the at least one static address selection terminal of each data bus node integrated circuit,
• detecting said state of the at least one static address selection terminal in each data bus node integrated circuit by determining an electrical property of said passive electronic component connected thereto,
• determining a node address identifier in each data bus node integrated circuit taking said detected state of the at least one static address selection terminal into account,
• receiving and/or transmitting data over said data bus in accordance with a first communication protocol using said node address identifier determined in each data bus node integrated circuit for identification of said data bus node integrated circuit,
• configuring a further node address identifier for each data bus node integrated circuit taking data received by said data bus node integrated circuit using said first communication protocol into account, and
• receiving and/or transmitting data over said data bus in accordance with a second communication protocol using said further node address identifier for identification of each data bus node integrated circuit.