Managing reuse information with multiple translation stages

An apparatus comprising:

• a storage device configured to store memory pages including a first memory page retrieved from the storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space, where the attempt to retrieve the data in the first memory page from the physical address space is issued in response to a cache miss;
• an external memory system including:
• (1) a main memory controller coupled to main memory having the physical address space, and (2) a first cache configured to store a plurality of cache lines and to issue the cache miss after an attempt to retrieve the data in the first memory page from at least one of the cache lines;
• and
• a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor at a first access level and at least one guest operating system at a second access level;
• wherein the processor is configured to:
• at the second access level, translate from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space;
• at the second access level, determine reuse information for ranges of virtual addresses in the virtual address space based on estimated reuse of data stored within the virtual address space;
• at the first access level, translate from the intermediate physical addresses to physical addresses in the physical address space of the main memory;
• at the first access level, determine reuse information for ranges of intermediate physical addresses in the intermediate physical address space based on estimated reuse of data stored within the intermediate physical address space;
• and
• process reuse information determined at different access levels to store cache lines in selected portions of the first cache.