US 2016/0259689 A1Published application

Managing reuse information in caches

AssigneeCavium, Inc.

InventorShubhendu Sekhar Mukherjee

Life of this patent

Estimating the term…

Loading patent…

Abstract

Address translation and caching is managed using a processor that includes at least one CPU configured to run a hypervisor and at least one guest operating system. The managing includes: translating from virtual addresses to intermediate physical addresses; translating from the intermediate physical addresses to physical addresses; determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages; storing the determined reuse information independently from: (1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses; and using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of a first cache.

Claims22

Dependent claims

A method for managing address translation and caching, the method comprising:

retrieving a first memory page from a storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space of a main memory of an external memory system;
issuing the attempt to retrieve the data in the first memory page in response to a cache miss issued after an attempt to retrieve the data in the first memory page from a first cache line of a first cache of the external memory system;
and
managing address translation and caching from a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor and at least one guest operating system, the managing including:
translating from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space;
translating from the intermediate physical addresses to physical addresses in the physical address space of the main memory;
determining reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages;
storing the determined reuse information independently from:
(1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses;
and
using the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of the first cache.

8 more elements

An apparatus comprising:

a storage device configured to store memory pages including a first memory page retrieved from the storage device in response to a page fault issued after an attempt to retrieve data in the first memory page from a physical address space, where the attempt to retrieve the data in the first memory page from the physical address space is issued in response to a cache miss;
an external memory system including:
(1) a main memory controller coupled to main memory having the physical address space, and (2) a first cache configured to store a plurality of cache lines and to issue the cache miss after an attempt to retrieve the data in the first memory page from at least one of the cache lines;
and
a processor that includes (1) at least one memory management unit coupled to the external memory system, and (2) at least one central processing unit configured to run a hypervisor and at least one guest operating system;
wherein the processor is configured to:
translate from virtual addresses in a virtual address space to intermediate physical addresses in an intermediate physical address space;
translate from the intermediate physical addresses to physical addresses in the physical address space of the main memory;
determine reuse information for memory pages based on estimated reuse of cache lines of data stored within the memory pages;
store the determined reuse information independently from:
(1) any bits used to indicate virtual addresses, (2) any bits used to indicate intermediate physical addresses, and (3) any bits used to indicate physical addresses;
and
use the stored reuse information to store cache lines in a selected group of multiple groups of cache lines of the first cache.

10 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/638,266Filed 4 Mar 2015
Published: 8 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

G06F 11/1402
Error detection or correction of the data by redundancy in operations: saving, restoring, recovering or retrying
G06F 12/0802
In hierarchically structured memory systems, e.g. virtual memory systems: addressing of a memory level in which the access to the desired data or…
G06F 12/0895
Caches characterised by their organisation or structure: of parts of caches, e.g. directory or tag array
G06F 12/1045
Using associative or pseudo-associative address translation means, e.g. translation look-aside buffer [TLB]: associated with a data cache

Family

US 9,720,773 B2Related patent
US 2016/0259689 A1This patent

From the US filing history. Foreign family members aren’t listed.

Timeline

Citations

Open elsewhere

Building an agent or pulling many patents? Use the API or MCP server instead of scraping pages. Get an API key