US 2016/0259687 A1Published application

Storage system

AssigneeHitachi, Ltd.

InventorsTomohiro YOSHIHARA, Akira YAMAMOTO, Shigeo HOMMA, Junji OGAWA

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Abstract

The storage system according to the present invention comprises a controller, and multiple storage device constituting a RAID group. When storing write data to multiple discontinuous areas within stripes of a storage device, the storage system transmits a new data transmission command containing information for specifying the multiple discontinuous areas and a write data to the storage device, and thereafter, receives an intermediate parity generated from multiple write data and data before update of the multiple write data from the storage device, and then transmits the received intermediate parity and an intermediate parity transmission command to the storage device storing the parity. Thereafter, a data commitment command containing information for specifying multiple discontinuous areas is transmitted to multiple storage devices, and the storage device storing the parity generates a parity after update from the received intermediate parity and a parity before update corresponding to the intermediate parity, and stores the parity after update in a storage media.

Claims14

Dependent claims

A storage system comprising a controller having one or more processors, and multiple storage devices having storage media, the multiple storage devices constituting a RAID group, wherein

the RAID group is configured to store a parity calculated from data stored within a given range of n number of storage devices constituting the RAID group to the given range of one of said storage devices constituting the RAID group;
when multiple write data is stored in a first storage device of the n number of storage devices, the processor is configured to:
transmit to the first storage device a new data transmission command containing information capable of specifying multiple areas within the given range in the first storage device, and the multiple write data;
receive multiple first intermediate parities generated from the multiple write data and data before update of the multiple write data from the first storage device;
transmit an intermediate parity transmission command containing information. capable of specifying the multiple areas, and the multiple first intermediate parities, to a storage device storing the parity corresponding to the multiple write data;
transmit a data commitment command containing information capable of specifying the multiple areas to the multiple storage devices;
and
when the storage device storing the parity receives the data commitment command, it is configured to generate a parity after update based on the first intermediate parity and the parity before update stored in multiple areas of the storage device storing the parity.

5 more elements

The storage system according to claim 2, wherein

when the processor transmits the intermediate parity transmission command to a storage device storing the parity,
when transmitting the first intermediate parity received from the first storage device, it is configured to create and transmit the intermediate parity transmission command containing a first row number;
when transmitting the second intermediate parity received from the second storage device, it is configured to create the intermediate parity transmission command containing a second row number that differs from the first row number;
and
when the storage device storing the parity receives the intermediate parity transmission command containing the first row number and the intermediate parity transmission command containing the second row number, it is configured to map both the first intermediate parity and the second intermediate parity to the area contained in the intermediate parity transmission command, and store the same.

2 more elements

A storage device comprising one or more storage media and a controller:

wherein
for each logical area in a logical address space provided by the storage device, the controller is configured to map a first address within the storage media storing data of the logical area to a second address of a new area storing data for update of the logical area, and manage the same;
when the controller receives a new data transmission command containing information for specifying multiple said logical areas arranged discontinuously in the logical address space and update data of the multiple logical areas from an external device connected to the controller,
the controller is configured to:
store update data of the multiple logical areas in the storage media;
and
map an address within the storage media storing the update data as the second address for each of the multiple logical areas specified by the information for specifying the multiple logical areas;
when the controller receives a read command for reading data of the logical area from the external device, it is configured to read the data from a first address within the storage media storing data of the logical area, and sends the same to the external device;
and
when the controller receives an intermediate parity reception command containing information for specifying the multiple logical areas arranged discontinuously in the logical address space from the external device,
the controller is configured to calculate an exclusive OR of data read from the first address and the second address mapped to each of the multiple logical areas, and return the computed exclusive OR to the external device,
wherein the controller is composed to map multiple third addresses within the storage media storing an intermediate parity for generating a parity after update of data of the logical area to each logical area in a logical address space provided by the storage device;
and
when the controller receives information for specifying multiple logical areas arranged discontinuously in the logical address space, an intermediate parity transmission command containing row number k, and the multiple intermediate parities corresponding to the multiple logical areas from the external device,
the controller is configured to store the multiple intermediate parities in the storage media;
and
map an address in the storage media storing the intermediate parity corresponding to the logical area as a k-th third address for each of the logical areas.

14 more elements

Dependencies are inferred from the claim text.

Facts

Application: 14/426,716Filed 28 Mar 2014
Published: 8 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification6 codes

G06F 11/1076
Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's: parity data used in redundant arrays of…
G06F 3/0619
Improving the reliability of storage systems: in relation to data integrity, e.g. data losses, bit errors
G06F 3/064
Organizing or formatting or addressing of data: management of blocks
G06F 3/0688
Plurality of storage devices: non-volatile semiconductor memory arrays

Family

US 9,778,986 B2Related patent
US 2016/0259687 A1This patent

From the US filing history. Foreign family members aren’t listed.

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