Memory device, memory system and method of operating the same

A synchronous dynamic random access memory (DRAM) device comprising:

• a memory cell array including a plurality of memory cells;
• a parity region including a plurality of memory cells;
• a clock pin receiving a clock signal;
• a plurality of data pins receiving write data;
• a plurality of command/address pins receiving command/address signals comprising a write command and a write address, wherein the write address indicates a location of the memory cell array for the write data to be written into;
• a data masking pin receiving a data masking signal, wherein the data masking signal indicates a first portion of the write data to be masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
• a write command determination unit configured to determine whether the write command is a normal write command or a read modify write command, and to produce a first control signal if the write command is the read modify write command;
• a data modulation unit configured to generate modulation data in response to the first control signal by reading the first portion of memory cell array to produce a first read data and replacing the first portion of write data with the first read data, wherein the size of the modulation data is equal to the size of the write data;
• an error correction code (ECC) engine configured to generate a parity of the modulation data if the write command is the read modify write command;
• and
• a writing unit configured to write at least a second portion of the write data and the parity of the modulation data into the memory cell array and the parity region respectively if the write command is the read modify write command, wherein the second portion of the write data is a portion of write data excepting the first portion of the write data.

A method of writing data in a synchronous dynamic random access (SDRAM) memory device including an error correction code (ECC) engine, the method comprising:

• receiving command/address signals comprising a write command, a write address and write data, wherein the write data is written into a memory cell array of the memory device based on the write command and the write address;
• receiving a data masking signal indicating a first portion of the write data to be masked, wherein the first portion of the write data is addressed by the write address to be written into a first portion of the memory cell array;
• determining whether the write command is a read modify write command or a normal write command based on at least one of the command/address signals;
• reading the first portion of the memory cell array to produce a first read data if the write command is the read modify write command;
• generating modulation data by replacing the first portion of the write data with the first read data, wherein the size of the modulation data is equal to the size of the write data;
• encoding a parity of the modulation data by using the ECC engine;
• and
• writing at least a second portion of the write data and the parity of the modulation data into the memory cell array and a parity region respectively if the write command is the read modify write command, wherein the second portion of the write data is a portion of write data excepting the first portion of the write data