Hardware and runtime coordinated load balancing for parallel applications
AssigneeAdvanced Micro Devices, Inc.
InventorsPeter Bailey, Indrani Paul, Manish Arora
Life of this patent
Estimating the term…
Abstract
A method of balancing execution rates for a plurality of parallel program loops being executed concurrently by a processor may include estimating a completion time for each program loop of the plurality of program loops, determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops, and decreasing the difference by adjusting an execution rate of the first program loop.
Claims20
A method, comprising:
- estimating a completion time for each program loop of a plurality of program loops executed concurrently by a processor;
- determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops;
- and
- decreasing the difference by adjusting an execution rate of the first program loop.
An apparatus, comprising:
- one or more loop progress buffers configured to store loop progress information for each of a plurality of program loops executed concurrently by a set of processing cores;
- a runtime system coupled with one or more loop progress buffers and configured to:
- estimate a completion time for each of the plurality of program loops based on the loop progress information;
- determine a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops;
- and
- a power management unit coupled with the runtime system, wherein the power management unit is configured to decrease the difference by adjusting an execution rate of the first program loop.
A non-transitory computer-readable medium storing instructions that when executed by a processor, cause the processor to perform a method comprising:
- estimating a completion time for each program loop of a plurality of program loops executed concurrently by the processor;
- determining a difference between the estimated completion time of a first program loop of the plurality of program loops and the estimated completion time of a second program loop of the plurality of program loops;
- and
- decreasing the difference by adjusting an execution rate of the first program loop.
Dependencies are inferred from the claim text.