Instruction fetch device and instruction fetching method

Abstract

Provided is an instruction fetch device including a plurality of PC buffers which store addresses of next to-be-executed instructions in respective branches; a plurality of instruction buffers which store to-be-executed instructions and indexes of the PC buffers associated with the respective instructions among the PC buffers; and a fetch unit which fetches the to-be-executed instructions one by one from a program memory to sequentially store the fetched to-be-executed instructions in the instruction buffers and represents the next to-be-executed instruction in a current branch by using the PC buffer hiving one index among the PC buffers before branch prediction is hit, wherein the number of the PC buffers is less than the number of the instruction buffers.

Dependencies are inferred from the claim text.