Impedance-based flow control for a two-wire interface system with variable frame length

A method, comprising:

• in a transmitting device, serializing a plurality of general purpose input/output (GPIO) signals into a first VGI frame and into a second VGI frame, wherein the first VGI frame and the second VGI frame each ends with a stop bit having an initial portion and a remaining portion;
• transmitting an initial portion of the first VGI frame over a transmit pin on the transmitting device to a receive pin for a receiving device responsive to a plurality of cycles of an oversampling clock signal, wherein the initial portion of the first VGI frame begins with a start bit and ends prior to the first VGI frame's stop bit;
• transmitting the initial portion of the first VGI frame's stop bit over the transmit pin by charging the transmit pin through a low output impedance to a power supply voltage responsive to at least one cycle of the oversampling clock signal;
• transmitting the remaining portion of the first VGI frame's stop bit over the transmit pin by charging the transmit pin through a high output impedance to the power supply voltage responsive to a plurality of cycles of the oversampling clock signal;
• and
• responsive to a detection that a voltage for the transmit pin did not drop below a threshold voltage during the transmission of the remaining portion of first VGI frame's stop bit, transmitting an initial portion of the second VGI frame over the transmit pin to the receive pin for the receiving device responsive to a plurality of cycles of the oversampling clock signal.

An integrated circuit, comprising:

• a first processor;
• a plurality of general purpose input output (GPIO) pins;
• a transmit pin;
• a GPIO interface configured to receive a transmit set of GPIO signals from the first processor and to transmit a first portion of the transmit set over the GPIO pins to a remote second processor,
• a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the GPIO interface into at least a first virtual GPIO (VGI) frame including a stop bit;
• a transmit buffer configured to transmit an initial portion of the first VGI frame's stop bit over the transmit pin through a low output impedance responsive to at least one cycle of an oversampling clock signal and to transmit a remaining portion of first VGI frame's stop bit through a high output impedance responsive to a plurality of cycles of the oversampling clock signal;
• and
• means for comparing a voltage for the transmit pin to a threshold voltage for making a flow control decision with regard to a subsequent transmission of a second VGI frame by the transmit buffer.

An integrated circuit, comprising:

• a first processor;
• a transmit pin;
• a GPIO interface configured to receive a transmit set of GPIO signals from the processor and to transmit a first portion of the transmit set over a plurality of GPIO pins to a remote second processor;
• a finite state machine configured to serialize a remaining second portion of the transmit set of GPIO signals from the GPIO interface into a plurality of virtual GPIO bits in a first virtual GPIO (VGI) frame and in a second VGI frame, wherein the first VGI frame and the second VGI frame each ends with a stop bit, and wherein the stop bit has a width that is wider than a width for each of the virtual GPIO bits;
• a transmit buffer configured to transmit an initial portion of the first VGI frame's stop bit over the transmit pin through a low output impedance responsive to at least one cycle of an oversampling clock signal and to transmit a remaining portion of first VGI frame's stop bit through a high output impedance responsive to a plurality of cycles of the oversampling clock signal;
• and
• a transmit control circuit configured to command the transmit buffer to transmit an initial portion of the second VGI frame responsive to a determination that a voltage for the transmit pin was above a threshold voltage during the transmission of the remaining portion of the first VGI frame's stop bit.

A method, comprising:

• in a transmitting device, serializing a plurality of general purpose input/output (GPIO) signals into a plurality of virtual GPIO (VGI) bits included in a first VGI frame and in a second VGI frame, wherein the first VGI frame and the second VGI frame each ends with a stop bit having an initial portion and a remaining portion, and wherein each VGI bit has a first width and each stop bit has a second width, and wherein the second width is greater than the first width;
• transmitting an initial portion of the first VGI frame over a transmit pin on the transmitting device to a receive pin for a receiving device responsive to a plurality of cycles of an oversampling clock signal, wherein the initial portion of the first VGI frame begins with a start bit and ends prior to the first VGI frame's stop bit;
• transmitting the initial portion of the first VGI frame's stop bit over the transmit pin by charging the transmit pin through a low output impedance to a power supply voltage responsive to at least one cycle of the oversampling clock signal;
• transmitting the remaining portion of the first VGI frame's stop bit over the transmit pin by charging the transmit pin through a high output impedance to the power supply voltage responsive to a plurality of cycles of the oversampling clock signal;
• and
• responsive to a detection that a voltage for the transmit pin did not drop below a threshold voltage during the transmission of the remaining portion of first VGI frame's stop bit, transmitting an initial portion of the second VGI frame over the transmit pin to the receive pin for the receiving device responsive to a plurality of cycles of the oversampling clock signal.