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US 2016/0259562 A1Published application
Dynamic Cache Sharing Based on Power State
AssigneeIntel Corporation
InventorsRyan D. Wells, Michael J. Muchnick, Chinnakrishnan S. Ballapuram
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Abstract
The present invention discloses a method comprising: sending cache request; monitoring power state; comparing said power state; allocating cache resources; filling cache; updating said power state; repeating said sending, said monitoring, said comparing, said allocating, said filling, and said updating until workload is completed.
Claims21
(canceled)
A system on chip (SoC) comprising:
- a first compute engine comprising a central processing unit;
- a second compute engine comprising a graphics processing unit;
- a cache coupled to the first compute engine and the second compute engine;
- cache allocation logic associated with a way mask coupled to the cache and the first compute engine and the second compute engine, the way mask partitioned into ways, wherein some ways are dedicated to only one of the first compute engine and the second compute engine and other ways are shared between the first compute engine and the second compute engine;
- and
- a power control unit to monitor a power state of the first compute engine and the second compute engine and to update the way mask based on the power state of the first compute engine and the second compute engine.
3 more elements
A method comprising:
- sending a cache request;
- monitoring a power state of a first compute engine and a power state of a second compute engine;
- comparing the power state of the first compute engine and the power state of the second compute engine;
- allocating cache resources of a cache;
- filling the cache;
- updating the power state of the first compute engine and the power state of the second compute engine;
- and
- repeating the sending, the monitoring, the comparing, the allocating, the filling, and the updating until a workload is completed.
5 more elements
An apparatus comprising:
- a single die including a central processing unit (CPU) and a graphics processing unit (GPU), the single die further including a shared cache memory coupled to the CPU and the GPU, cache allocation logic associated with a way mask partitioned into a plurality of ways, wherein at least two of the plurality of ways are dedicated to the CPU and at least one of the plurality of ways is dedicated to the GPU and other ways of the plurality of ways are to be dynamically shared between the CPU and the GPU, and a power control unit to monitor a power state of the CPU and the GPU and to update the way mask based on the power state of the CPU and the GPU.
Dependencies are inferred from the claim text.