Systems and methods for implementing power collapse in a memory
AssigneeQUALCOMM Incorporated
InventorsAdam Edward NEWHAM, Kenneth David EASTON, Rashid Ahmed Akbar ATTAR
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AssigneeQUALCOMM Incorporated
InventorsAdam Edward NEWHAM, Kenneth David EASTON, Rashid Ahmed Akbar ATTAR
Estimating the term…
A power management system for stack memory thread tasks according to some examples of the disclosure may include a non-collapsible memory region, a collapsible memory region configured below the non-collapsible memory region, a memory management unit in communication with the non-collapsible memory region and the collapsible memory region, the memory management unit operable to allocate a portion of the non-collapsible memory region and a portion of the collapsible memory region to a thread task upon initialization of the thread task and power down the portion of the collapsible memory region allocated to the thread task upon receiving a power down command.
A power management system for thread tasks, comprising:
A method of powering down a memory, comprising:
A non-transitory computer-readable memory to store instructions that when executed on a system cause the system to perform a process, the process comprising:
Dependencies are inferred from the claim text.