Dynamic clock rate control for power reduction
AssigneeSanDisk Technologies LLC
InventorReed P. Tidwell
Life of this patent
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Abstract
A pipeline system may adjust clock rates of variable-rate clock signals sent to different processing circuit blocks in a pipeline based on their respective, individual input and output buffer fill levels and processor busy statuses. Variable-rate clock generation circuitry may generate the variable-rate clock signals based on a common clock signal. Additionally, the variable-rate clock generation circuitry may set or adjust the rates of variable-rate clock signals linearly in evenly-spaced increments and decrements.
Claims33
An electronic pipeline system comprising:
- a pipeline comprising a plurality of processing circuit blocks configured to process data and communicate the processed data in a main data flow of the pipeline using buffers;
- de-rating value generation circuitry configured to:
- monitor fill levels of the buffers;
- and
- generate de-rating values based on the fill levels, wherein each of the de-rating values corresponds to one of a plurality of fractions of a rate of a fixed-rate clock signal;
- variable-rate clock generation circuitry configured to:
- receive the de-rating values from the de-rating value generation circuitry and the fixed-rate clock signal;
- generate a plurality of variable-rate clock signals based on the de-rating values;
- and
- send the plurality of variable-rate clock signals to the plurality of processing circuit blocks.
A method of generating a clock signal for a pipeline, the method comprising:
- receiving, with a de-rating value generator, fill level information from at least one of an input buffer or an output buffer associated with a processing circuit block of the pipeline;
- determining, with the de-rating value generator, a fraction of a first rate of a first clock signal based on the fill level information, wherein the fraction comprises one among a plurality of fractions;
- sending, with the de-rating value generator, a de-rating value corresponding to the fraction to clock generation circuitry;
- generating, with the clock generation circuitry, a second clock signal at a second rate, wherein the second rate comprises the fraction of the first rate;
- and
- sending, with the clock generation circuitry, the second clock signal to the processing circuit block.
Clock generation circuitry for a pipeline, the clock generation circuitry comprising:
- first circuitry configured to:
- receive feedback information from the pipeline, wherein the feedback information comprises fill level information of input and output buffers associated with processing circuit blocks of the pipeline;
- and
- determine a plurality of fractions of a rate of a fixed-rate clock signal for a plurality of variable-rate clock signals based on the feedback information;
- and
- second circuitry configured to:
- generate the plurality of variable-rate clock signals, each at one of the plurality of fractions of the rate of the fixed-rate clock signal determined by the first circuitry;
- and
- send the plurality of variable-rate clock signals to the processing circuit blocks of the pipeline.
Dependencies are inferred from the claim text.