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US 2016/0259352 A1Published application
Semiconductor device
AssigneeKabushiki Kaisha Toshiba
InventorToshiyuki KOUCHI
Life of this patent
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Abstract
A semiconductor device of one embodiment includes semiconductor chips. While the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.
Claims20
A semiconductor device comprising:
- semiconductor chips, wherein
- while the semiconductor device is receiving a power supply and a chip enable signal which is negated, all external terminals of the semiconductor chips are at the same logic level.
A semiconductor device comprising:
- semiconductor chips, each of which comprises
- a first terminal at a first side,
- a second terminal at a second side opposite to the first terminal, and
- a logic circuit which generates a logic level of inversion of a logic level at the first terminal at the second terminal, wherein
- while the semiconductor device is receiving a power supply and a chip enable signal which is negated, the first and second terminals of each of the semiconductor chips are at the same logic level.
2 more elements
A semiconductor device comprising:
- a substrate having a first surface and a second surface opposite to the first surface;
- a first terminal on the first surface;
- a second terminal on the second surface;
- a logic circuit which generates a logic level of inversion of the logic level at the first terminal at the second terminal;
- a latch storing the same logic level as the logic level at the first terminal;
- and
- a controller which disables the logic circuit after the latch starts the storing of the same logic level as the logic level at the first terminal.
4 more elements
A semiconductor device comprising:
- semiconductor chips which are stacked and coupled through external terminals, wherein
- while the semiconductor device is receiving a power supply and a chip enable signal which is negated, all the external terminals of the semiconductor chips are at the same logic level.
Dependencies are inferred from the claim text.