Phase Locked Loop with Sub-harmonic Locking Prevention Functionality

A method for operating a phase-locked loop (PLL), comprising:

• generating, by a loop filter, a filter output signal based at least on a charge output signal;
• generating, by a voltage controlled oscillator, an oscillator output signal with a frequency corresponding to the filter output signal;
• generating, by a divider, a divider clock signal by performing a frequency division on the oscillator output signal, the divider clock signal having a same phase as the oscillator output signal but a frequency different than the oscillator output signal;
• and
• generating, by a phase frequency detector, the charge output signal to charge a sampling capacitor during a first time period set to prevent locking of the PLL at a frequency that is a sub-harmonic of a frequency of the oscillator output signal.

A non-transitory computer-readable medium storing a representation of a phase-locked loop (PLL), the PLL comprising:

• a loop filter comprising a sampling capacitor and a holding capacitor coupled in parallel via a switching element, the loop filter configured to generate a filter output signal based at least on a charge output signal indicating a first time period during which the sampling capacitor is charged;
• a voltage controlled oscillator (VCO) coupled to the loop filter and configured to generate an oscillator output signal with a frequency corresponding to the filter output signal;
• a divider coupled to the VCO to receive the oscillator output signal, the divider configured to perform frequency division on the oscillator output signal to generate a divider clock signal having a same phase as the oscillator output signal but a frequency different than the oscillator output signal;
• and
• a phase frequency detector coupled to the divider to receive the divider clock signal, the phase frequency detector configured to generate the charge output signal based on a phase difference between the divider clock signal and a reference clock signal, the phase frequency detector further configured to prevent locking of the PLL at a sub-harmonic of a frequency of the oscillator output signal.