Magnetic memory with high thermal budget

A method of forming a memory cell comprising:

• forming a select unit on a substrate, wherein the select unit comprises a transistor having
• a first source/drain (S/D) region,
• a second S/D region, and
• a gate between the first and second S/D regions;
• forming a dielectric layer on the substrate covering the select unit, wherein the dielectric layer includes a storage pad coupled to the first S/D region;
• forming a storage unit on the storage pad, wherein the storage unit comprises
• forming a bottom electrode,
• forming a fixed layer disposed over the bottom electrode, wherein the fixed layer comprises a hard layer disposed over a base layer, the base layer promotes face-centered cubic (FCC) structure along (111) orientation to increase perpendicular magnetic anisotropy, the base layer comprises
• a wetting layer,
• a seed layer, wherein the seed layer comprises
• a first seed layer,
• a roughness smoother to improve surface smoothness of the first seed layer, and
• a second seed layer formed over the roughness smoother,
• wherein the roughness smoother improves surface smoothness of the second seed layer, wherein improved surface smoothness of the seed layer improves surface smoothness of the hard layer to improve thermal endurance,
• forming at least a first tunneling barrier layer over the hard layer,
• forming a storage layer over the first tunneling barrier layer, and
• forming a top electrode over the storage layer;
• and
• forming a bitline coupled to the top electrode layer.

A storage unit of a memory cell comprising:

• a bottom electrode;
• a fixed layer disposed over the bottom electrode, wherein the fixed layer comprises a hard layer disposed over a base layer, the base layer promotes face-centered cubic (FCC) structure along (111) orientation to increase perpendicular magnetic anisotropy, the base layer comprises
• a wetting layer,
• a seed layer, wherein the seed layer comprises
• a first seed layer,
• a roughness smoother to improve surface smoothness of the first seed layer, and
• a second seed layer disposed over the roughness smoother, wherein the roughness smoother improves surface smoothness of the second seed layer, wherein improved surface smoothness of the seed layer improves surface smoothness of the hard layer to improve thermal endurance;
• at least a first tunneling barrier layer disposed over the hard layer;
• a storage layer disposed over the first tunneling barrier layer;
• and
• a top electrode disposed over the storage layer.