FETs and Methods for Forming the Same

A structure comprising:

• a substrate having a major surface;
• a transistor structure on the substrate and extending in a direction normal to the major surface, the transistor structure comprising a first source/drain region, a channel region, and a second source/drain region, the channel region being on the first source/drain region in the direction normal to the major surface, the second source/drain region being on the channel region in the direction normal to the major surface, the channel region having a sidewall surface, a deviation angle of the sidewall surface from the direction normal to the major surface exceeding 2 degrees;
• and
• a gate structure surrounding the channel region in a plane perpendicular to the direction normal to the major surface.

A structure comprising:

• a fin on a substrate;
• a first source/drain region and a second source/drain region in the fin, a portion of the fin being disposed between the first source/drain region and the second source/drain region, an upper part of the portion of the fin having a V-shaped recess;
• a channel region over the V-shaped recess;
• a void between the upper part of the portion of the fin and the channel region;
• a gate dielectric in the void;
• and
• a gate electrode in the void.