Integrated circuits with fets having nanowires and methods of manufacturing the same

A method of fabricating a nanowire comprising:

• epitaxially forming a stack over a substrate, wherein the stack comprises a silicon germanium layer and a silicon layer, and wherein the silicon germanium layer has a first silicon germanium layer volume;
• condensing the stack to produce a second silicon germanium layer volume less than the first silicon germanium layer volume;
• and
• forming a nanowire from the silicon germanium layer.

An integrated circuit comprising:

• a fin;
• a gate overlying the fin;
• a nanowire within the fin, wherein the nanowire comprises germanium with a germanium concentration of from about 70 weight percent to about 90 weight percent;
• a nanowire insulator overlying the nanowire, wherein the nanowire insulator comprises silicon dioxide;
• and
• a gate dielectric layer between the fin and the gate.