Power semiconductor device
AssigneeMitsubishi Electric Corporation
InventorKatsumi NAKAMURA
Life of this patent
Estimating the term…
Abstract
A semiconductor substrate includes a drift region and a collector region. The drift region is provided across an active area, an interface area, and an edge termination area. The collector region is provided only in the active area and forms part of a second surface. An emitter electrode is provided in the active area and contacts a first surface of the semiconductor substrate. A collector electrode is provided on the second surface of the semiconductor substrate and contacts the collector region.
Claims16
A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:
- a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including
- a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type,
- a collector region that is provided only in said active area, forms part of said second surface, and has a second conductivity type different from said first conductivity type, and
- a buffer layer that has a portion located between said drift region and said collector region in said active area, has said first conductivity type, and has an impurity concentration higher than an impurity concentration in said drift region;
- an emitter electrode that is provided in said active area and contacts said first surface of said semiconductor substrate;
- and
- a collector electrode that is provided on said second surface of said semiconductor substrate and contacts said collector region, wherein
- said active area has a MIS structural portion in which a MIS structural cell is disposed and a non-MIS structural portion in which no MIS structural cell is disposed, and
- said buffer layer and said collector electrode contact each other on said second surface of said semiconductor substrate in said non-MIS structural portion.
(canceled)
A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:
- a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including
- a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type, and
- a well region that is provided on said first surface, is at least partially included in said interface area, has an end portion on said first surface between said interface area and said edge termination area, and has a second conductivity type different from said first conductivity type;
- a first electrode that is provided in said active area and contacts said first surface of said semiconductor substrate, said first surface having an electrical path formed thereon, said electrical path connecting said first electrode to said end portion of said well region with a region of said second conductivity type, said electrical path having a resistance region that is formed of said well region and has a width L, the width L being set so as to suppress a local temperature rise in one of both ends of said resistance region by sharing the temperature rise at said both ends during an operation of said power semiconductor device;
- and
- a second electrode contacting said second surface of said semiconductor substrate.
A power semiconductor device having an active area, an interface area provided around a periphery of said active area, and an edge termination area provided around a periphery of said interface area, said power semiconductor device comprising:
- a semiconductor substrate having a first surface and a second surface opposite to said first surface, said first surface and said second surface each being located across said active area, said interface area, and said edge termination area, said semiconductor substrate including
- a drift region that is provided across said active area, said interface area, and said edge termination area and has a first conductivity type,
- a collector region that is provided only in said active area, forms part of said second surface, and has a second conductivity type different from said first conductivity type, and
- a buffer layer that has a portion located between said drift region and said collector region in said active area, has said first conductivity type, and has an impurity concentration higher than an impurity concentration in said drift region;
- an emitter electrode that is provided in said active area and contacts said first surface of said semiconductor substrate;
- and
- a collector electrode that is provided on said second surface of said semiconductor substrate and contacts said collector region, wherein
- said semiconductor substrate includes a well region that is provided on said first surface, is at least partially included in said interface area, has an end portion on said first surface between said interface area and said edge termination area, and has said second conductivity type, and
- in said interface area, a contact at the same potential as the emitter electrode to said well region is not provided.
Dependencies are inferred from the claim text.