MAGNETIC RANDOM ACCESS MEMORY (MRAM) BIT CELLS EMPLOYING SOURCE LINES (SLs) AND/OR BIT LINES (BLs) DISPOSED IN MULTIPLE, STACKED METAL LAYERS TO REDUCE MRAM BIT CELL RESISTANCE

A method of fabricating a magnetic random access memory (MRAM) bit cell in an integrated circuit (IC), comprising:

• forming an access transistor in a semiconductor layer, the access transistor comprising a gate, a source, and a drain;
• forming a magnetic tunnel junction (MTJ) in a metal layer disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;
• forming a drain-side connection column in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;
• forming a bit line in at least one metal layer above the semiconductor layer coupled to the second end electrode of the MTJ;
• and
• forming a source line in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the source of the access transistor.

An integrated circuit (IC) comprising at least one magnetic random access memory (MRAM) bit cell, the at least one MRAM bit cell, comprising:

• an access transistor disposed in a semiconductor layer of the IC, the access transistor comprising a gate, a source, and a drain;
• a magnetic tunnel junction (MTJ) disposed in a metal layer in the IC disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;
• a drain-side connection column disposed in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;
• a source line disposed in at least one metal layers in the IC above the semiconductor layer and coupled to the source of the access transistor;
• and
• a bit line disposed in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the second end electrode of the MTJ.

A method of fabricating a magnetic random access memory (MRAM) bit cell in an integrated circuit (IC), comprising:

• forming an access transistor in a semiconductor layer, the access transistor comprising a gate, a source, and a drain;
• forming a magnetic tunnel junction (MTJ) in a metal layer disposed above the semiconductor layer, the MTJ comprising a first end electrode and a second end electrode;
• forming a drain-side connection column in at least one metal layer in the IC above the semiconductor layer coupling the drain of the access transistor to the first end electrode of the MTJ;
• forming a source line in at least one metal layer above the semiconductor layer coupled to the source of the access transistor;
• and
• forming a bit line in a plurality of stacked metal layers in the IC above the semiconductor layer coupled to the second end electrode of the MTJ.