US 2016/0254283 A1 · ARRAY SUBSTRATE AND ITS MANUFACTURING METHOD, DISPLAY DEVICE

Abstract

An array substrate includes a base substrate (10) and a gate line (11) and a data line (12) provided on the base, the gate line (11) and the data line (12) define a pixel unit, and in the pixel unit, a thin film transistor (13) is provided, the thin film transistor (13) includes a gate electrode (131), a gate insulation layer (132), an active layer (133), a source electrode (134) and a drain electrode (135). The gate insulation layer (132) includes a first gate insulation portion (1321) and a second gate insulation portion (1322), the gate electrode (131) is located between the first gate insulation portion (1321) and the second gate insulation portion (1322), and the second gate insulation portion (1322) is located between the gate electrode (131) and the active layer (133). The array substrate further includes a conductive pad (114), and a first via (15) corresponding to the conductive pad (114) is provided in the gate insulation layer (132) at both sides of the gate line (11), and the data line (12) is connected to the conductive pad (114) through the first via (15). The array substrate is capable of improving the definition, the resolution and the aperture ratio of a display device. A manufacturing method for an array substrate and a display device including such an array substrate are also disclosed.

Claims20

Dependent claims

An array substrate comprising:

a base substrate, and a gate line and a data line which are provided on the base substrate to be intersected with each other, wherein the gate line and the data line define a pixel unit, the pixel unit is provided with a thin film transistor therein, the thin film transistor includes a gate electrode, a gate insulation layer, an active layer, a source electrode and a drain electrode, the gate insulation layer includes a first gate insulation portion and a second gate insulation portion, the gate electrode is located between the first gate insulation portion and the second gate insulation portion, the second gate insulation portion is located between the gate electrode and the active layer;
a conductive pad located at an intersection position of the gate line and the data line;
and
a first via corresponding to the conductive pad provided in the gate insulation layer at both sides of the gate line, wherein the data line is connected to the conductive pad through the first via.

1 more element

A manufacturing method for an array substrate comprising:

forming a gate line, a gate electrode, a gate insulation layer, an active layer, a data line, a source electrode, a drain electrode and a conductive pad on a base substrate, wherein the gate insulation layer includes a first gate insulation portion and a second gate insulation portion;
the gate electrode is located between the first gate insulation portion and the second gate insulation portion, and the second gate insulation portion is located between the gate electrode and the active layer;
the conductive pad is located at an intersection position between the gate line and the data line, and a first via corresponding to the conductive pad is formed in the gate insulation layer at both sides of the gate line, and the data line is connected to the conductive pad through the first via.

Dependencies are inferred from the claim text.

Array substrate and its manufacturing method, display device

Life of this patent

Array substrate and its manufacturing method, display device

Life of this patent

Abstract

Claims20