US 2016/0254269 A1 · Array Of Non-volatile Memory Cells With ROM Cells

Abstract

A memory device that includes a plurality of ROM cells each having spaced apart source and drain regions formed in a substrate with a channel region therebetween, a first gate disposed over and insulated from a first portion of the channel region, a second gate disposed over and insulated from a second portion of the channel region, and a conductive line extending over the plurality of ROM cells. The conductive line is electrically coupled to the drain regions of a first subgroup of the ROM cells, and is not electrically coupled to the drain regions of a second subgroup of the ROM cells. Alternately, a first subgroup of the ROM cells each includes a higher voltage threshold implant region in the channel region, whereas a second subgroup of the ROM cells each lack any higher voltage threshold implant region in the channel region.

Claims16

Dependent claims

(canceled)

Dependencies are inferred from the claim text.

Facts

Application

14/639,063Filed 4 Mar 2015

Priority

CN 201510089866.927 Feb 2015

Published

1 Sep 2016

Term ends

Not estimatedThe source records don’t support an estimate.

Classification12 codes

H10B 41/35
Characterised by the memory core region: with a cell select transistor, e.g. NAND
H10B 20/34
Having the source region and the drain region on the same level, e.g. lateral transistors: source electrode or drain electrode programmed
H10B 20/36
Having the source region and the drain region on the same level, e.g. lateral transistors: gate programmed, e.g. different gate material or no gate
H10B 20/38
Having the source region and the drain region on the same level, e.g. lateral transistors: doping programmed, e.g. mask ROM

Array Of Non-volatile Memory Cells With ROM Cells

Life of this patent

Array Of Non-volatile Memory Cells With ROM Cells

Life of this patent

Abstract

Claims16