Memory metal scheme

A method of fabricating a memory, the method comprising:

• forming a first portion of a first control line and a first portion of a second control line in a first metal layer, wherein the first control line is isolated from the second control line;
• forming a second portion of the first line in a second metal layer over the first metal layer, the second portion of the first line coupled to the first portion of the first control line;
• and
• forming a second portion of the second line in a third metal layer over the second metal layer, wherein the third metal layer substantially overlaps the second metal layer.

A method of fabricating a memory array, the method comprising:

• designing a plurality of first layout sections in a row direction, each of the first layout section of the plurality of first layout sections comprises a first control line and a second control line in a first metal layer, a lower conductive line in a second metal layer coupled to the first control line in the first metal layer, and an upper conductive line in a third metal layer coupled to the second control line in the first metal layer, wherein the first control line is isolated from the second control line;
• and
• inserting a second layout section into every N-th first layout section of the plurality of first layout sections, N being a positive integer equal to or greater than 2, the second layout section comprising the first control line and the second control line in the first metal layer, a lower conductive line in the second metal layer coupled to the first control line in the first metal layer, and an upper conductive line in the third metal layer coupled to the second control line in the second metal layer, wherein
• the lower conductive line in the first layout section is isolated from the lower conductive line in the second layout section;
• and
• the second control line couples the upper conductive line in the first layout section and the upper conductive line in the second layout section.