System-on-chip devices and methods of designing a layout therefor

A layout design method comprising:

• providing a layout pattern for forming a system-on-chip device, in which a plurality of standard cells are provided, wherein:
• the providing of the layout pattern comprises providing a first metal layout defining a first metal layer,
• the first metal layout comprises:
• a first pattern extending in a first direction;
• and
• a second pattern spaced apart from the first pattern in the first direction to extend in a second direction crossing the first direction,
• the first and second patterns, respectively, comprise first and second sidewalls facing each other, and
• a distance between the first sidewall and the second sidewall is in a range from about 1 to about 1.2 times a minimum separation distance given by a design rule for a layout.

A logic cell comprising:

• a substrate with an active pattern for the logic cell, the active pattern being extending in a first direction parallel to a top surface of the substrate;
• and
• a first metal layer electrically connected to the active pattern, wherein:
• the first metal layer comprises:
• a first metal line having a first width in the first direction;
• a second metal line that is spaced apart from the first metal line in a second direction crossing the first direction by about a minimum spacing according to a layout design rule and having a second width in the second direction that is about one-half the first width or less and about the same as a minimum line width according to the layout design rule, and
• a third metal line that is spaced apart from the first metal line on an opposite side of the first metal line with respect to the second direction by the minimum spacing and having the second width in the second direction, wherein:
• at least one of the first to third metal lines is electrically connected to the active pattern through a first via extending through a first insulating layer disposed between the active pattern and the first metal layer, and
• the first metal line is not electrically connected to either of the second and third metal lines through metal connectivity.