Methods of Making Integrated Circuit Assembly with Faraday Cage

A method comprising:

• forming an active device in a first region of a semiconductor layer of a wafer, the wafer having an insulating layer, the semiconductor layer, and a substrate layer, the insulating layer having a first surface and a second surface, the second surface of the insulating layer being below the first surface of the insulating layer, the substrate layer contacting the second surface of the insulating layer, the semiconductor layer having a first surface and a second surface, the first surface of the semiconductor layer contacting the first surface of the insulating layer;
• forming a first electrically conductive interconnect layer with an electrically conductive ring;
• forming a second electrically conductive interconnect layer with a first electrically conductive plate above the electrically conductive ring and the first region of the semiconductor layer;
• removing the substrate layer from the second surface of the insulating layer;
• forming a third electrically conductive interconnect layer with a second electrically conductive plate below the electrically conductive ring, the insulating layer, and the first region of the semiconductor layer;
• and
• forming a plurality of electrically conductive vias electrically coupling the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate;
• wherein the electrically conductive ring, the first electrically conductive plate, the second electrically conductive plate, and the plurality of electrically conductive vias form a Faraday cage around the active device.

A method performed with respect to a semiconductor wafer, the wafer having a semiconductor layer above an insulating layer and a substrate layer below the insulating layer, the method comprising:

• front-side processing on the wafer, including:
• forming an active device in the semiconductor layer, forming a first electrically conductive interconnect layer with an electrically conductive ring, and forming a second electrically conductive interconnect layer with a first electrically conductive plate above the electrically conductive ring and the active device;
• and
• back-side processing on the wafer subsequent to the front-side processing, the back-side processing including:
• removing the substrate layer, forming a third electrically conductive interconnect layer with a second electrically conductive plate below the electrically conductive ring, the insulating layer, and the active device, and forming a plurality of electrically conductive vias electrically coupling the electrically conductive ring to the first electrically conductive plate and to the second electrically conductive plate.

A method performed with respect to a semiconductor on insulator (SOI) wafer, the wafer including a semiconductor layer disposed above an insulating layer and a substrate layer disposed below the insulating layer, the method comprising:

• forming a transistor in the semiconductor layer;
• forming a first conductive interconnect layer having a ring above the transistor;
• forming a second conductive interconnect layer having a first conductive plate above the ring and the transistor;
• after forming the transistor and first and second conductive interconnect layers, removing at least part of the substrate layer;
• and
• after removing at least part of the substrate layer, performing back-side processing operations including forming a third conductive interconnect layer with a second conductive plate below the ring, the insulating layer, and the transistor, and forming a plurality of vias coupling the ring to the first conductive plate and to the second conductive plate, wherein the first conductive plate, the ring, the second conductive plate, and the plurality of vias surround the transistor.