Capping layer for improved deposition selectivity

An integrated chip, comprising:

• a first etch stop layer disposed over a semiconductor substrate;
• an extreme low-k (ELK) dielectric layer comprising a lower ELK dielectric layer disposed over the first etch stop layer, and an upper ELK dielectric layer disposed in contact with the lower ELK dielectric layer;
• one or more metal layer structures disposed within the ELK dielectric layer;
• a first capping layer disposed over the ELK dielectric layer at positions between the one or more metal layer structures and having a density greater a density of the upper ELK dielectric layer;
• and
• a second capping layer disposed over the one or more metal layer structures.

An integrated chip, comprising:

• a dielectric layer disposed over a substrate;
• one or more metal layer structures disposed within the dielectric layer;
• a first capping layer located over the dielectric layer at positions between the one or more metal layer structures;
• and
• a second capping layer located over the one or more metal layer structures, wherein the second capping layer has a greater thickness in areas overlying the one or more metal layer structures than in areas not overlying the one or more metal layer structures.