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US 2016/0254221 A1Published application
Semiconductor package and manufacturing method thereof
AssigneeAmkor Technology, Inc.
InventorsIn Ho Kim, Jae Yun Kim, Kyeong Sool Seong
Life of this patent
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Abstract
A semiconductor package and a method of making a semiconductor package. As non-limiting examples, various aspects of this disclosure provide various semiconductor packages, and methods of making thereof, that comprise a conductive layer that comprises an anchor portion extending through at least one dielectric layer.
Claims20
A semiconductor device comprising:
- a semiconductor die comprising a die passivation layer and a conductive pad exposed through an aperture in the die passivation layer;
- a first dielectric layer (DL) on the die passivation layer and comprising:
- a first DL aperture through which the conductive pad is exposed;
- and
- a second DL aperture through which the die passivation layer is exposed;
- a conductive layer (CL) on the first dielectric layer and comprising:
- a first CL portion in the first DL aperture;
- a second CL portion in the second DL aperture;
- and
- a third CL portion;
- a second dielectric layer (DL) on the conductive layer and comprising a third DL aperture through which the third CL portion is exposed;
- and
- an interconnection structure electrically connected to the third CL portion through the third DL aperture.
10 more elements
A semiconductor device comprising:
- a conductive pad;
- a first dielectric layer (DL) comprising a first DL aperture through which the conductive pad is exposed;
- a second dielectric layer (DL) on the first dielectric layer and comprising a plurality of DL anchor apertures through which the first dielectric layer is exposed;
- a conductive layer (CL) on the second dielectric layer and comprising a plurality of CL anchor portions, each in a respective one of the DL anchor apertures;
- and
- a third dielectric layer (DL) on the conductive layer and comprising a DL aperture through which a portion of the conductive layer is exposed.
3 more elements
A semiconductor device comprising:
- a first dielectric layer (DL);
- second dielectric layer (DL) comprising an anchor aperture exposing the first dielectric layer;
- and
- a conductive layer (CL) on the second dielectric layer and comprising:
- a first CL end region electrically contacting another conductive layer;
- a second CL end region electrically contacting an interconnection structure of the semiconductor device;
- an extension region extending between the first and second CL end regions;
- and
- an anchor region in the anchor aperture and contacting the first DL.
6 more elements
Dependencies are inferred from the claim text.