Semiconductor memory device and memory system
AssigneeKabushiki Kaisha Toshiba
InventorsYusuke OCHI, Masanobu SHIRAKAWA
Life of this patent
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Abstract
A semiconductor memory device includes a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell, a second stack of memory cells above the substrate, the second stack including a third memory cell, a word line connected to the first, second, and third memory cells, and a controller configured to output data stored in the first memory cell and data stored in the third memory cell during a first cycle, and output data stored in the second memory cell during a second cycle that is different from the first cycle.
Claims20
A semiconductor memory device comprising:
- a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell;
- a second stack of memory cells above the substrate, the second stack including a third memory cell;
- a word line connected to the first, second, and third memory cells;
- and
- a controller configured to output data stored in the first memory cell and data stored in the third memory cell during a first cycle, and output data stored in the second memory cell during a second cycle that is different from the first cycle.
A memory system comprising:
- a semiconductor memory device that includes a plurality of memory cells divided into groups, a word line connected to the memory cells, and a control unit configured to output data from the memory cells one group at a time;
- and
- a controller that performs error correction for data output from each group,
- wherein when the controller fails to correct errors in a group through the error correction, the controller transmits a re-reading command, first information indicating a shift amount of a voltage to be applied to the word line during the re-reading, and second information identifying a group for which error correction failed, to the semiconductor memory device.
A method of executing a read operation in a semiconductor memory device having a first stack of memory cells above a substrate, the first stack including a first memory cell and a second memory cell above the first memory cell, a second stack of memory cells above the substrate, the second stack including a third memory cell, and a word line connected to the first, second, and third memory cells, said method comprising:
- reading first data stored in the first memory cell and data stored in the third memory cell and outputting the first data during a first cycle;
- and
- reading second data stored in the second memory cell and outputting the second data during a second cycle that is different from the first cycle.
Dependencies are inferred from the claim text.