US 2016/0254055 A1Published application

Nonvolatile semiconductor memory device

AssigneeKabushiki Kaisha Toshiba

InventorGou FUKANO

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Abstract

A nonvolatile semiconductor memory device includes a memory cell array having multiple blocks each with a plurality of memory strings. Each memory string has multiple memory cells connected in series between first and second selection transistors. The device further includes a row decoder, a block decoder, first and second signal line groups, and a switch circuit. The row decoder has transfer transistors through which voltages are supplied to the selection transistors. The block decoder supplies a selection signal that indicates whether the first group or the second group has been selected. The first and second signal line groups are connected to the selection transistors of the memory strings that are in the respective first and second memory blocks of the first and second groups. The switch circuit connects the first and second signal line groups to the respective first and second memory blocks of the selected group.

Claims15

Dependent claims

A semiconductor memory device, comprising:

a memory cell array including a first block and a second block, the first block including a first memory string, a second memory string, and a third memory string, the second block including a fourth memory string, a fifth memory string, and a sixth memory string, each of the first to third memory strings including a first selection transistor and a plurality of first memory cells connected in series, each of the fourth to sixth memory strings including a second selection transistor and a plurality of second memory cells connected in series;
a plurality of first transistors connected to gates of the plurality of first memory cells of the first to third memory strings;
a second transistor connected to a gate of the first selection transistor of the first memory string;
a third transistor connected to a gate of the first selection transistor of the second memory string;
a fourth transistor connected to a gate of the first selection transistor of the third memory string;
a plurality of fifth transistors connected to gates of the plurality of second memory cells of the fourth to sixth memory strings;
a sixth transistor connected to a gate of the second selection transistor of the fourth memory string;
a seventh transistor connected to a gate of the second selection transistor of the fifth memory string;
and
an eighth transistor connected to a gate of the second selection transistor of the sixth memory string,
wherein gates of the first transistors, the second transistor, the third transistor, the fourth transistor, the fifth transistors, the sixth transistor, the seventh transistor and the eighth transistor are electrically connected to a first line.

8 more elements

A semiconductor memory device, comprising:

a memory cell array including a first block comprising a plurality of first memory cells connected in series to a first selection transistor, a plurality of second memory cells connected in series to a second selection transistor, and a plurality of third memory cells connected in series to a third selection transistor;
a plurality of first transistors connected to gates of the plurality of first memory cells, the plurality of second memory cells, and the plurality of third memory cells;
a second transistor connected to a gate of the first selection transistor;
a third transistor connected to a gate of the second selection transistor;
a fourth transistor connected to the gate of the second selection transistor;
and
a fifth transistor connected to agate of the third selection transistor,
wherein gates of the first transistors, the second transistor, the third transistor, the fourth transistor, and the fifth transistor are electrically connected to a first line.

5 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/151,883Filed 11 May 2016
Priority: JP 2012-20950124 Sep 2012
Published: 1 Sep 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification11 codes

G11C 16/0483
Using variable threshold transistors, e.g. FAMOS: comprising cells having several storage transistors connected in series
G11C 8/08
Arrangements for selecting an address in a digital store: word line control circuits, e.g. drivers, boosters, pull-up circuits, pull-down…
G11C 8/10
Arrangements for selecting an address in a digital store: decoders
G11C 8/12
Arrangements for selecting an address in a digital store: group selection circuits, e.g. for memory block selection, chip selection, array selection

Family

Application13/784,512Continuation · filed 4 Mar 2013
Application14/688,664Continuation · filed 16 Apr 2015
Application15/151,883Continuation
US 2014/0086001 A1Published application
US 2015/0294722 A1Published application
US 9,053,765 B2Related patent
US 9,368,213 B2Related patent
US 9,666,284 B2Related patent
US 2016/0254055 A1This patent

From the US filing history. Foreign family members aren’t listed.

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