Nonvolatile semiconductor memory device and method of manufacturing the same
AssigneeKabushiki Kaisha Toshiba
InventorsKarin TAKAYAMA, Takeshi Murata
Life of this patent
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Abstract
According to an embodiment, a nonvolatile semiconductor memory device comprises: a memory string including a plurality of memory cells connected in series; a first select gate transistor connected to one end of this memory string; and a first voltage application circuit that controls this first select gate transistor. The first select gate transistor includes a plurality of first transistors connected in series. The first voltage application circuit performs application of a voltage so as to render the plurality of first transistors in a conductive state synchronously.
Claims19
A semiconductor memory device, comprising:
- a memory string including a plurality of memory cells connected in series;
- a first select gate transistor connected to one end of the memory string;
- and
- a first voltage application circuit that controls the first select gate transistor,
- the first select gate transistor including a plurality of first transistors connected in series, and
- the first voltage application circuit performing application of a voltage so as to render the plurality of first transistors in a conductive state synchronously.
A method of manufacturing a semiconductor memory device, the semiconductor memory device comprising:
- a plurality of memory cells provided in a first region on a semiconductor layer;
- and a plurality of first transistors provided in a second region on the semiconductor layer, the method comprising:
- stacking on the semiconductor layer a first insulating layer which will be a gate insulating layer of the memory cell and the first transistor;
- stacking on the first insulating layer a floating gate electrode formation layer which will be a floating gate electrode of the memory cell and the first transistor;
- and
- dividing the floating gate electrode formation layer in the first direction, in the first region and the second region.
A semiconductor memory device, comprising:
- a semiconductor layer extending in a first direction;
- a plurality of first floating gate electrodes that are arranged in a first direction along the semiconductor layer and face the semiconductor layer;
- a plurality of first control gate electrodes respectively facing the plurality of first floating gate electrodes;
- and
- a first voltage application circuit that applies a first voltage to the plurality of first control gate electrodes with an identical timing.
Dependencies are inferred from the claim text.