Static random access memory cell having improved write margin for use in ultra-low power application

A static random access memory circuit, comprising:

• a pair of inverters cross coupled to each other to form two storage nodes;
• one or more write access switches electrically coupled between write bit lines and two storage nodes and operable, in response to a signal on a write word line, to connect the two storage nodes to the write bit lines, where the write bit lines are used to write values to the two storage nodes during a write operation;
• and
• two or more supply switches electrically coupled between a supply voltage and the pair of inverters and operable, in response to a signal on at least one of the write bit lines, to selectively connect the supply voltage to at least one of the inverters in the pair of inverters.

A static random access memory circuit, comprising:

• a pair of inverters cross coupled to each other to form two storage nodes;
• two write bit lines electrically connected to the two storage nodes and operable to write values to the two storage nodes;
• a first write access transistor having a drain terminal coupled to one of the two storage nodes and a gate terminal coupled to one of the two write bit lines;
• a second write access transistor having a drain terminal coupled to the other of the two storage nodes and a gate terminal coupled to other of the two write bit lines;
• a third write access transistor having a drain terminal coupled to each of the source terminals for the first and second write access transistors, a gate terminal coupled to the write word line, and a source terminal coupled to ground;
• a first pair of supply transistors electrically coupled between a supply voltage and one of the storage nodes and operable, in response to a signal on one of the write bit lines, to connect the supply voltage to the one storage node;
• and
• a second pair of supply transistors electrically coupled between the supply voltage and other of the storage nodes and operable, in response to a signal on other of the write bit lines, to connect the supply voltage to other storage node, wherein, during a write operation, the supply transistors operate to cut off the supply voltage to the inverter in the pair of inverters having a charged state.