US 2016/0253976 A1 · SHIFT REGISTER

Abstract

Disclosed is a shift register capable of preventing charges supplied to a Q node to turn on a pull-up transistor for outputting a scan pulse from leaking outwards. The shift register includes a plurality of stages connected to gate lines formed at a panel. Each stage includes a scan signal generator for generating a scan pulse or a turn-off signal, a scan pulse controller for generating a Q-node control signal for generation of the scan pulse, a Q-node adjuster for preventing the Q-node control signal from leaking outwards during supply of the Q-node control signal to a Q-node connected to the scan signal generator, and a turn-off signal controller for transferring a Qb-node control signal for generation of the turn-off signal to the scan signal generator via a Qb-node when no scan pulse is generated from the scan signal generator.

Claims15

Dependent claims

A shift register comprising:

a plurality of stages connected to gate lines formed at a panel,
wherein each of the stages comprises:
a scan signal generator for generating a scan pulse or a turn-off signal;
a scan pulse controller for generating a Q-node control signal for generation of the scan pulse;
a Q-node adjuster for preventing the Q-node control signal from leaking outwards during supply of the Q-node control signal to a Q-node connected to the scan signal generator;
and
a turn-off signal controller for transferring a Qb-node control signal for generation of the turn-off signal to the scan signal generator via a Qb-node when no scan pulse is generated from the scan signal generator.

4 more elements

A shift register comprising:

a plurality of stages connected to gate lines formed at a display panel,
wherein each of the stages comprises:
a scan pulse controller for generating a Q-node control signal at a Q-node;
a turn-off signal controller for generating a Qb-node control signal at a Qb-node, the Qb-node control signal being an inverse of the Q-node control signal;
a scan signal generator for generating a scan pulse based on the Q-node control signal at the Q-node or a turn-off signal based on the Qb-node control signal at the Qb-node;
and
a Q-node adjuster circuit comprising:
a first switching element controlled by a first control signal and connected between the Q-node and a first connection node, and
a second switching element controlled by the first control signal and connected between the first connection node and a second control signal;
wherein the Q-node adjuster circuit is configured to supply to the first connection node a third control signal in relation to the first control signal to ensure turn off of the first switching element during supply of the Q-node control signal to the Q-node.

7 more elements

Dependencies are inferred from the claim text.

Shift register

Life of this patent

Shift register

Life of this patent

Abstract

Claims15