Program profiler circuit, processor, and program counting method
AssigneeFujitsu Limited
InventorTakatoshi FUKUDA
Life of this patent
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AssigneeFujitsu Limited
InventorTakatoshi FUKUDA
Estimating the term…
A program profiler circuit includes: a stack having a first storage region for stacking, when an instruction to call a subroutine is detected, a head address of the subroutine and for unstacking a lastly stacked head address when a restoration instruction to return to a source from which the subroutine is called is detected; a matching determining unit that has a plurality of second storage regions in which head addresses of subroutines are registered and is configured to output region information indicating a second storage region having registered therein a head address that matches the head address lastly stacked by the stack processing unit; and an accumulator that has a plurality of accumulation regions corresponding to the plurality of second storage regions and is configured to increment with a predetermined value to a value stored in an accumulation region corresponding to the region information output from the matching determining unit.
A program profiler circuit comprising:
A processor comprising:
A program counting method comprising:
Dependencies are inferred from the claim text.