Apparatuses and methods including error correction code organization

An apparatus comprising:

• first memory cells associated with a first access line;
• second memory cells associated with a second access line;
• and
• a controller to:
• store first data in the first memory cells;
• store second data in a first memory cell group of second memory cells;
• store at least a portion of an error correction code associated with the second data in a second memory cell group of the second memory cells;
• and
• store a portion of an error correction code associated with the first data in a third memory cell group of the second memory cells, wherein the controller is configured to concurrently store the at least a portion of the error correction code associated with the second data and the portion of the error correction code associated with the first data.

An apparatus comprising:

• first memory cells associated with a first access line;
• second memory cells associated with a second access line;
• and
• a controller to:
• retrieve information from the first memory cells;
• generate data from the information using a first portion of error correction code associated with the data, the first portion of error correction code associated with the data being included in the information;
• retrieve a second portion of the error correction code associated with the data from the second memory cells if the data is unsuccessfully generated from the information using the first portion of error correction code associated with the data;
• and
• generate data using the first portion of error correction code associated with the data and the second portion of error correction code associated with the data.