Watchdog Timer
AssigneeMicrochip Technology Incorporated
InventorKeith Curtis
Life of this patent
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Abstract
A microcontroller may comprise a central processing unit coupled with a plurality of peripheral devices through a system bus; and a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further having logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer.
Claims32
A watchdog timer unit configured to define a first and a second watchdog time period, wherein the watchdog timer unit is configured, after activation of the watchdog timer unit, to automatically select the first watchdog time period until a first clear watchdog signal has been received whereupon the watchdog timer unit switches to the second watchdog time period.
A microcontroller comprising:
- a central processing unit coupled with a plurality of peripheral devices through a system bus;
- and
- a watchdog timer unit receiving a clear watchdog signal and being configured to generate a watchdog timeout signal for resetting the microcontroller, wherein the watchdog timer unit is further configured to define a first and a second watchdog timeout period through a first and a second timer, respectively, further comprising logic to select the first or the second timer, wherein the clear watchdog signal resets the first and second timer.
A method for monitoring the execution of a program in a microcontroller through a watchdog timer unit defining a time period which after expiration resets the microcontroller wherein expiration of the time period is prevented by periodically resetting the watchdog timer unit, the method comprising:
- after activation of the watchdog timer unit, the watchdog timer unit automatically starts a first watchdog time period until a first clear watchdog signal has been received;
- generating a first watchdog reset signal by a central processing unit of the microcontroller;
- and
- upon receipt of the first clear watchdog signal and following watchdog reset signals, the watchdog timer unit automatically starts a second watchdog time period which is different than the first watchdog time period.
Dependencies are inferred from the claim text.