Error Detection Circuitry For Use With Memory

A method, comprising:

• receiving a data word for storage to a row of a memory array;
• generating one or more check bits based on the data word;
• storing the data word and the one or more check bits to the row;
• performing a detection of one or more bit errors in the stored data word using inline error detection circuitry coupled to the row;
• and
• correcting the one or more bit errors in the stored data word using error correction circuitry.

An integrated circuit, comprising:

• a memory array, comprising:
• a plurality of rows of memory cells, wherein a respective row is configured to store a horizontal data word and a horizontal parity bit corresponding to the horizontal data word;
• and
• a plurality of columns of memory cells, wherein a respective column is configured to store a vertical data word and a vertical parity bit corresponding to the vertical data word;
• and
• a plurality of error detection circuitry, comprising:
• inline horizontal error detection circuitry coupled to the respective row and configured to generate a horizontal flag bit value if the inline horizontal error detection circuitry detects one or more bit errors in the horizontal data word stored in the respective row;
• and
• inline vertical error detection circuitry coupled to the respective column and configured to generate a vertical flag bit if the inline vertical error detection circuitry detects one or more bit errors in the vertical data word stored in the respective column.