Register File Having a Plurality of Sub-Register Files
AssigneeImagination Technologies Limited
InventorHugh Jackson
Life of this patent
Estimating the term…
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AssigneeImagination Technologies Limited
InventorHugh Jackson
Estimating the term…
Register files for use in an out-of-order processor that have been divided into a plurality of sub-register files. The register files also have a plurality of buffers which are each associated with one of the sub-register files. Each buffer receives and stores write operations destined for the associated sub-register file which can be later issued to the sub-register file. Specifically, each clock cycle it is determined whether there is at least one write operation in the buffer that has not been issued to the associated sub-register file. If there is at least one write operation in the buffer that has not been issued to the associated sub-register file, one of the non-issued write operations is issued to the associated sub-register file. Each sub-register file may also have an arbitration logic unit which resolves conflicts between read and write operations that want to access the associated sub-register file in the same cycle by prioritizing read operations unless a conflicting write instruction has reached commit time.
A register file for an out-of-order processor, the register file comprising:
An out-of-order processor comprising:
A method of reading and writing to a register file of an out-of-order processor, the register file comprising a plurality of sub-register files, each sub-register file comprising at least one physical register, the method comprising:
Dependencies are inferred from the claim text.