Crossing pipelined data between circuitry in different clock domains

A non-transitory machine-readable medium having stored thereon a machine readable dataset description of a machine, that when processed, causes a layout processing system to generate a circuit layout description used to manufacture an integrated circuit comprising:

• a first circuit configured to be clocked by a first clock, the first circuit operable to operate at a first frequency to:
• store an element of control information in a control queue;
• and
• store an element of data in a data queue. after a pipeline delay characterized by a pre-set number of clock events of the first clock;
• a second circuit configured to be clocked by a second clock, and operable to operate at a different frequency than said first frequency;
• and
• a counter operable to be initialised to an initial value and to be updated during subsequent clocking;
• wherein the second circuit is configured to read the element of control information from the control queue responsive to the value of the counter reaching a pre-determined value, and to read the element of data from the data queue after the pre-set number of clock events have occurred for the second clock after the control information is read.

A non-transitory computer-readable medium having stored thereon computer executable instructions, which when executed cause at least one processor to:

• store an element of control information in a control queue according to a first clock operating at a first frequency;
• store an element of data in a data queue, after a pipeline delay characterized by a pre-set number of clock events of the first clock;
• initialise a counter to an initial value;
• update the counter with clock events;
• and
• responsive to the counter reaching a pre-determined value, read the element of control information from the control queue according to a second clock, operating at a second frequency different than said first frequency, and then read the element of data from the data queue after the pre-set number of clock events have occurred for the second clock.