Circuits and methods of testing a device under test using the same

A circuit for testing a device under test (DUT), the circuit comprising:

• first and second DUT nodes connected to the DUT;
• first and second voltage nodes free from connection with each other;
• a first transistor including a first terminal connected to the first voltage node, a second terminal connected to the first DUT node, and a third terminal;
• a second transistor including a first terminal connected to the second voltage node, a second terminal connected to the second DUT node, and a third terminal free from connection with the third terminal of the first transistor;
• and
• a control unit including a pair of ports, each of which is connected to the third terminal of a respective one of the first and second transistors, and configured to control operations of the first and second transistors.

A method of testing a device under test (DUT) connected between first and second DUT nodes, the method comprising:

• generating a first set of control signals;
• and
• in response to the first set of control signals:
• disconnecting a first voltage node from the first DUT node;
• connecting a second voltage node to the first DUT node;
• periodically connecting and disconnecting a third voltage node to and from the second DUT node at a predetermined frequency;
• disconnecting a fourth voltage node from the second DUT node when the third voltage node is connected to the second DUT node;
• and
• connecting the fourth voltage node to the second DUT node when the third voltage node is disconnected from the second DUT node.