Supperlattice buffer structure for gallium nitride transistors

A method for manufacturing a transistor, said method comprising:

• forming a first strained layer superlattice (SLS) layer over a substrate;
• forming a first buffer layer over the first SLS layer, wherein the first buffer layer has a high resistance relative to the first SLS layer;
• forming a second SLS layer over the first buffer layer;
• forming a second buffer layer over the second SLS layer, wherein the second buffer layer has a high resistance relative to the second SLS layer;
• and
• forming a group III-V heterojunction over the second buffer layer.

A transistor comprising:

• a silicon substrate;
• first and second strained layer superlattice (SLS)/buffer pairs stacked in that order over the silicon substrate, wherein the first and second SLS/buffer pairs include corresponding SLS layers and corresponding buffer layers arranged over the corresponding SLS layers, wherein the SLS layers include alternating layers of aluminum nitride (AlN) and gallium nitride (GaN), and wherein the buffer layers include GaN layers doped with carbon or iron;
• a channel layer of undoped GaN arranged over the second SLS/buffer pair;
• and
• an active layer arranged over and directly abutting the channel layer, wherein the active layer includes aluminum gallium nitride (AlGaN), and wherein the channel and active layers collectively define a heterojunction.