Power integrated devices, electronic devices and electronic systems including the same

A power integrated device comprising:

• a channel region disposed in a first region of a semiconductor layer;
• a source region disposed in a second region of the semiconductor layer;
• a drift region disposed in a third region of the semiconductor layer, wherein the channel region is disposed between the source region and the drift region in a first direction;
• a drain region disposed in the drift region;
• a stacked gate including a gate insulation layer and a gate electrode and extending from over the channel region to over the drift region;
• a plurality of deep trench field insulation layers each of which is disposed in the drift region, and between the stacked gate and the drain region in the first direction;
• and
• a plurality of stacked gate extension portions which extend from the stacked gate to over the plurality of deep trench field insulation layers in the first direction, respectively,
• wherein the plurality of deep trench field insulation layers are spaced apart from each other in a second direction,
• wherein the drift region has a different conductivity from the first region of a semiconductor layer,
• wherein each of the plurality of deep trench field insulation layers has a height greater than a width,
• wherein the height is measured in a third direction and the width is measured in the first direction, and
• wherein the third direction is perpendicular to each of the first and the second directions.