US 2016/0240622 A1Published application

Non-volatile memory device and manufacture of the same

AssigneeXinnova Technology Limited

InventorsDER-TSYR FAN, CHIH-MING CHEN, JUNG-CHANG LU

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Abstract

This disclosure discloses a non-volatile memory component and a manufacture method of the same. The non-volatile memory component includes a substrate, a first dielectric layer on the substrate, an erase gate (EG), a floating gate (FG) and a select gate (EG). The substrate includes a source region and a drain region. The erase gate (EG), the floating gate (FG) and the select gate (EG) are formed on the first dielectric layer. Additionally, non-volatile memory component includes a coupling dielectric layer formed in the intervals and the upper region of the erase gate (EG), the floating gate (FG) and the select gate (SG), and a coupling gate (CG) formed on the coupling dielectric layer.

Claims20

Dependent claims

A method for manufacturing a non-volatile memory component, comprising steps of:

(1) providing a substrate;
(2) forming a base dielectric layer on the substrate;
(3) forming a first polysilicon layer on the base dielectric layer;
(4) defining a first pattern opening and a second pattern opening on the first polysilicon layer and the base dielectric layer;
(5) forming a liner dielectric layer on the first polysilicon layer and the base dielectric layer;
(6) forming a sacrificial layer filled in the horizontal intervals between the first polysilicon layer and the liner dielectric layer;
(7) removing the first polysilicon layer within the first pattern opening;
(8) performing ion implantation within the first pattern opening;
(9) forming a first capping dielectric layer by oxidizing the first polysilicon layer and the base dielectric layer;
(10) forming a second polysilicon layer filled in the interval on the base dielectric layer within the first pattern opening;
(11) forming a second capping dielectric layer on the second polysilicon layer within the first pattern opening;
(12) forming a damascene trench with an interval formed by two damascene structures on the substrate;
wherein, one of the damascene structures is a stack made of the first capping dielectric layer, the first polysilicon layer and the base dielectric layer;
and the other damascene structure is a stack made of the second capping dielectric layer, the second polysilicon layer and the base dielectric layer;
(13) forming a third capping dielectric layer covering the two damascene structures and the damascene trench;
(14) forming a third polysilicon layer filled in the damascene trench covered by the third capping dielectric layer;
(15) forming a coupling dielectric layer on the third capping dielectric layer;
(16) selectively forming a fourth polysilicon layer on the coupling dielectric layer;
and
(17) defining a third pattern opening to perform ion implantation.

17 more elements

A non-volatile memory component, comprising:

a substrate having a surface nearby a source region and a drain region, and there is a channel region between the source region and the drain region;
a first dielectric layer, formed on the substrate;
wherein an erase gate (EG), a select gate (SG) and a floating gate (FG) are formed on the first dielectric layer, the erase gate (EG) is located above the source region while the select gate and the floating gate are located at the upper projection area of the channel region in the depth direction;
a second dielectric layer, formed on the first dielectric layer and wraps the erase gate (EG) and the select gate (SG) in;
wherein the floating gate (FG) is located between the adjacent second dielectric layers;
a coupling dielectric layer, covering the second dielectric layer and the floating gate (FG) unevenly;
and
a coupling gate (CG), formed on the coupling dielectric layer;
wherein, the first dielectric layer includes a first thickness within the first pattern opening, the first dielectric layer includes a second thickness under the projection area of the floating gate (FG) in the depth direction, and the first dielectric layer includes a third thickness under the projection region of the select gate (SG) in the depth direction;
wherein, the first thickness is thicker than the second thickness, and the second thickness thicker than the third thickness.

7 more elements

Dependencies are inferred from the claim text.

Facts

Application: 15/011,516Filed 30 Jan 2016
Priority: 16 Feb 2015
Published: 18 Aug 2016
Term ends: Not estimatedThe source records don’t support an estimate.

Classification8 codes

H10D 30/6892
Characterised by the shapes, relative sizes or dispositions of the floating gate electrode: having at least one additional gate other than the…
H10B 41/10
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the top-view layout
H10B 41/30
Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates: characterised by the memory core region
H10D 30/0411
Of FETs having insulated gates [IGFET]: of FETs having floating gates

Family

Application62/116,776Us provisional application · filed 16 Feb 2015
US 9,502,513 B2Related patent
US 2016/0240622 A1This patent

From the US filing history. Foreign family members aren’t listed.

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