Multi-layer interconnected spiral capacitor

A multi-layer capacitor, comprising:

• a first level planar capacitor, comprising a first level first trace and a first level second trace, configured above a plane;
• and
• a second level planar capacitor, spaced above the first level planar capacitor by a dielectric layer, comprising a second level first trace and a second level second trace, wherein the second level first trace is aligned above the first level first trace to form a first parallel plate capacitor, and the second level second trace is aligned above the first level second trace to form a second parallel plate capacitor;
• and
• a bridged-post inter-layer interconnector, comprising
• at least two first posts and at least two second posts, wherein the at least two first posts and the at least two first posts are configured to extend normal to the plane and through the dielectric layer,
• a first level first post coupler, arranged under the dielectric layer, configured to couple the at least two first posts together and to the first level first trace,
• a first level second post coupler, arranged under the dielectric layer, configured to couple the first level second trace to at least one of the at least two second posts,
• a second level second post coupler, arranged above second dielectric layer, configured to couple the at least two second posts together and to the second level first trace, and
• a second level first post coupler, arranged above second dielectric layer,
• configured to couple the second level second trace to at least one of the at least two first posts.

A multi-layer capacitor, comprising:

• a capacitor stack, wherein the capacitor stack comprises odd level spiral capacitors and even level spiral capacitors, each of the even level spiral capacitors spaced above a corresponding one of the odd level spiral capacitors, wherein each of the odd level spiral capacitors comprises an odd level first spiral winding and an odd level second spiral winding, the odd level first spiral winding and the odd level second spiral winding being interwound about a winding axis, wherein each of the even level spiral capacitors comprises an even level first spiral winding and an even level second spiral winding, the even level first spiral winding and the even level second spiral winding being interwound about the winding axis, and in a tracking alignment with the odd level first spiral winding and the odd level second spiral winding of an underlying one of the odd level spiral capacitors;
• and
• a bridged-post inter-layer interconnect, comprising at least two first posts, and at least two second posts, wherein the at least two first posts and the at least two second posts are configured to extend through the respective dielectric layers, wherein the bridged-post inter-layer interconnect further comprises
• adjacent each of the odd level spiral capacitors, an odd level first post coupler and an odd level second post coupler, wherein the odd level first post coupler is configured to couple the at least two first posts together and to the odd level first spiral winding of the odd level spiral capacitor, and the odd level second post coupler is configured to couple the odd level second spiral winding of the odd level spiral capacitor to at least one of the at least two second posts, and
• adjacent each of the even level spiral capacitors, an even level first post coupler and an even level second post coupler, wherein the even level second post coupler is configured to couple the at least two second posts together and to the even level first spiral winding of the even level spiral capacitor, and the even level first post coupler is configured to couple the even level second spiral winding of the even level spiral capacitor to at least one of the at least two first posts.

A multi-layer capacitor, comprising:

• a first level planar capacitor, comprising a first level first trace and a first level second trace, each extending above a plane;
• and
• a second level planar capacitor, spaced above the first level planar capacitor by a dielectric layer, comprising a second level first trace and a second level second trace, wherein the second level first trace is aligned above the first level first trace to form a first parallel plate capacitor, and the second level second trace is aligned above the first level second trace to form a second parallel plate capacitor;
• a third level planar capacitor, spaced above the second level planar capacitor by a second dielectric layer, comprising a third level first trace and a third level second trace, wherein the third level first trace is aligned above the second level first trace to form a third parallel plate capacitor, and wherein the third level second trace is aligned above the second level second trace to form a fourth parallel plate capacitor;
• a fourth level planar capacitor, spaced above the third level planar capacitor by a third dielectric layer, comprising a fourth level first trace and a fourth level second trace, wherein the fourth level first trace is aligned above the third level first trace to form a fifth parallel plate capacitor, and the fourth level second trace is aligned above the third level second trace to form a sixth parallel plate capacitor;
• and
• means for coupling, in parallel, the first level planar capacitor, the second level planar capacitor, the first parallel plate capacitor, the second parallel plate capacitor, the third parallel plate capacitor, the fourth parallel plate capacitor, the fifth parallel plate capacitor, and the sixth parallel plate capacitor.