Memory device, semiconductor device, and methods for producing memory device and semiconductor device

A memory device comprising:

• first pillar-shaped semiconductor layers,
• gate insulating films formed around the first pillar-shaped semiconductor layers,
• gate electrodes formed around the gate insulating films,
• gate lines connected to the gate electrodes,
• first diffusion layers formed in upper portions of the first pillar-shaped semiconductor layers,
• second diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, and
• a plurality of memory elements arranged in two or more rows and two or more columns and formed on the first diffusion layers, each memory element comprising a pillar-shaped phase change layer, a reset gate insulating film surrounding the pillar-shaped phase change layer, and a reset gate surrounding the reset gate insulating film,
• wherein the reset gates are connected in a row direction and in a column direction, and are heaters, and
• the pillar-shaped phase change layers are electrically insulated from the reset gates.

A method for producing a semiconductor device, the method comprising:

• a first step of forming fin-shaped semiconductor layers on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layers;
• a second step following the first step, the second step including forming a second insulating film around the fin-shaped semiconductor layers, depositing and planarizing a first polysilicon on the second insulating film, forming a second resist for forming gate lines, first pillar-shaped semiconductor layers, second pillar-shaped semiconductor layers, and a contact line so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layers extend, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layers so as to form first pillar-shaped semiconductor layers, first dummy gates formed of the first polysilicon, second pillar-shaped semiconductor layers, and second dummy gates formed of the first polysilicon;
• a third step following the second step, the third step including forming a fourth insulating film around the first pillar-shaped semiconductor layers, the second pillar-shaped semiconductor layers, the first dummy gates, and the second dummy gates, depositing a second polysilicon around the fourth insulating film, and etching the second polysilicon so as to allow the second polysilicon to remain on side walls of the first dummy gates, the first pillar-shaped semiconductor layers, the second dummy gates, and the second pillar-shaped semiconductor layers so as to form third dummy gates and fourth dummy gates;
• a fourth step of forming second diffusion layers in upper portions of the fin-shaped semiconductor layers, lower portions of the first pillar-shaped semiconductor layers, and lower portions of the second pillar-shaped semiconductor layers, forming a fifth insulating film around the third dummy gates and the fourth dummy gates, etching the fifth insulating film into a side wall shape so as to form side walls formed of the fifth insulating film, and forming a metal-semiconductor compound on the second diffusion layers;
• a fifth step following the fourth step, the fifth step including depositing and planarizing an interlayer insulating film, exposing upper portions of the first dummy gates, the second dummy gates, the third dummy gates, and the fourth dummy gates, removing the first dummy gates, the second dummy gates, the third dummy gates, and the fourth dummy gates, removing the second insulating film and the fourth insulating film, forming a gate insulating film around the first pillar-shaped semiconductor layers, around the second pillar-shaped semiconductor layers, and on an inner side of the fifth insulating film, forming a fourth resist for removing the gate insulating film around bottom portions of the second pillar-shaped semiconductor layers, removing the gate insulating film around the bottom portions of the second pillar-shaped semiconductor layers, depositing a metal, and etching back the metal so as to form gate electrodes and gate lines around the first pillar-shaped semiconductor layers and form contact electrodes and a contact line around the second pillar-shaped semiconductor layers;
• and
• a sixth step following the fifth step, the sixth step including depositing and planarizing a second interlayer insulating film to expose upper portions of the first pillar-shaped semiconductor layers, forming pillar-shaped phase change layers and lower electrodes on the exposed first pillar-shaped semiconductor layers, forming a reset gate insulating film that surrounds the pillar-shaped phase change layers and the lower electrodes, and forming a reset gate that surrounds the pillar-shaped phase change layers that function as memory devices.