Vertical cmos structure and method

A complementary transistor structure comprising:

• a lower portion of a column comprising crystalline germanium formed on a silicon substrate;
• a first gate surrounding and insulated from the lower portion of the column;
• an upper portion of the column formed on top of the lower portion of the column comprising indium arsenide;
• a second gate surrounding and insulated from the lower portion of the column;
• a first electrical contact to the upper portion of the column above the second gate;
• and
• a second electrical contact to the upper portion and lower portion of the column between the first and second gates.

A complementary transistor structure comprising:

• a first vertical nanowire extending from a substrate, the first vertical nanowire being a first semiconductor material;
• a second vertical nanowire extending from the first vertical nanowire, the first vertical nanowire being disposed between the second vertical nanowire and the substrate, the second vertical nanowire being a second semiconductor material different than the first semiconductor material;
• a first gate adjacent a first channel region of the first vertical nanowire;
• and
• a second gate adjacent a second channel region of the second vertical nanowire, a common source/drain region being interposed between the first gate and the second gate.