Integrated circuit packaging substrate, semiconductor package, and manufacturing method

A semiconductor package, comprising:

• an integrated circuit (IC) packaging substrate comprising:
• a main body;
• at least one first conductive line embedded in the main body;
• at least one second conductive line embedded in the main body;
• and
• at least one protrusion pad protruding from the main body, wherein at least a portion of an orthogonal projection of the protrusion pad on the main body overlaps an orthogonal projection of the first conductive line on the main body;
• and
• a semiconductor chip bonded to the IC packaging substrate and having a solder portion that is in electrical contact with the protrusion pad, wherein a width of the protrusion pad and a width of the first conductive line is determined to form a first spacing between the protrusion pad and the second conductive line.

A manufacturing method of a semiconductor package, the method comprising:

• determining a first spacing between a protrusion pad on at least one first conductive line of an integrated circuit (IC) packaging substrate of the semiconductor package and a second conductive line of the IC packaging substrate in accordance with a process deviation of the protrusion pad by a width of the protrusion pad and a width of the first conductive line;
• forming the first and second conductive lines, and the protrusion pad on a main body of the IC packaging substrate;
• and
• bonding a semiconductor chip of the semiconductor package to the IC packaging substrate, such that a solder portion of the semiconductor chip is in electrical contact with the protrusion pad of the IC packaging substrate.